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Unity Gain Stable, Ultralow Distortion, 1 nV/Hz Voltage Noise, High Speed Op Amp ADA4899-1
FEATURES
Unity gain stable Ultralow noise: 1 nV/Hz, 2.6 pA/Hz Ultralow distortion -117 dBc at 1 MHz High speed -3 dB bandwidth: 600 MHz (G = +1) Slew rate: 310 V/s Offset voltage: 230 V max Low input bias current: 100 nA Wide supply voltage range: 5 V to 12 V Supply current: 14.7 mA High performance pinout Disable mode
CONNECTION DIAGRAMS
ADA4899-1
DISABLE 1 FEEDBACK 2 -IN 3 +IN 4 NC = NO CONNECT
8 7 6 5
+VS VOUT NC -VS
05720-001
Figure 1. 8-Lead LFCSP_VD (CP-8)
ADA4899-1
FEEDBACK 1 -IN 2 +IN 3 -VS 4
8 7 6 5
DISABLE +VS VOUT -VS
05720-002
APPLICATIONS
A-to-D drivers Instrumentation Filters IF and baseband amplifiers DAC buffers Optical electronics
Figure 2. 8-Lead SOIC_N_EP (RD-8)
GENERAL DESCRIPTION
The ADA4899-1 is an ultralow noise (1 nV/Hz) and distortion (<-117 dBc @1 MHz) unity gain stable voltage feedback op amp, the combination of which makes it ideal for 16-bit and 18-bit systems. The ADA4899-1 features a linear, low noise input stage and internal compensation that achieves high slew rates and low noise even at unity gain. ADI's proprietary next generation XFCB process and innovative circuit design enable such high performance amplifiers. The ADA4899-1 drives 100 loads at breakthrough performance levels with only 15 mA of supply current. With the wide supply voltage range (4.5 V to 12 V), low offset voltage (230 V max), wide bandwidth (600 MHz), and slew rate (310 V/s), the ADA4899-1 is designed to work in the most demanding applications. The ADA4899-1 also features an input bias current cancellation mode, which reduces input bias current by a factor of 60. The ADA4899-1 is available in a 3 mm x 3 mm LFCSP and a 8-lead SOIC package. Both packages feature an exposed metal paddle that improves heat transfer to the ground plane. This is a significant improvement over traditional plastic packages. The ADA4899-1 is rated to work over the extended industrial temperature range, -40C to +125C.
-40 -50 G = +1 VS = 5V RL = 1k VOUT = 2V p-p
HARMONIC DISTORTION (dBc)
-60 -70 -80 -90
HD3 HD2
-100 -110
05720-071
-120 -130 0.1
1
10 FREQUENCY (MHz)
100
Figure 3. Harmonic Distortion vs. Frequency
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
ADA4899-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Connection Diagrams...................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications with 5 V Supply ..................................................... 3 Specifications with +5 V Supply ..................................................... 4 Absolute Maximum Ratings............................................................ 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Test Circuits..................................................................................... 12 Theory of Operation ...................................................................... 13 Packaging Innovation ................................................................ 13 DISABLE Pin .............................................................................. 13 Applications..................................................................................... 14 Unity Gain Operation................................................................ 14 Recommended Values for Various Gains................................ 14 Noise ............................................................................................ 15 ADC Driver................................................................................. 15 DISABLE Pin Operation ........................................................... 16 ADA4899-1 MUX ...................................................................... 16 Circuit Considerations .............................................................. 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19
REVISION HISTORY
10/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADA4899-1 SPECIFICATIONS WITH 5 V SUPPLY
TA = 25C, G = +1, RL = 1 k to ground, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN DISABLE Input Threshold Voltage Turn-Off Time Turn-On Time Input Current Input Current OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rise/Fall) Output Voltage Swing Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions VOUT = 25 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 5 V step VOUT = 2 V step fC = 500 kHz, VOUT = 2 V p-p fC = 10 MHz, VOUT = 2 V p-p f = 100 kHz f = 100 kHz, DISABLE pin floating f = 100 kHz, DISABLE pin = +VS Min Typ 600 80 35 310 50 -123/-123 -80/-86 1.0 2.6 5.2 35 5 -6 -0.1 3 0.05 85 4 7.3 4.4 -3.7 to +3.7 130 <2.4 100 40 17 -35 30/50 -3.65 to +3.65 -3.13 to +3.15 -3.7 to +3.7 -3.25 to +3.25 160/200 -48 12 16.2 2.1 21 230 -12 -1 0.7 Max Unit MHz MHz MHz V/s ns dBc dBc nV/Hz pA/Hz pA/Hz V V/C A A nA/C A dB k M pF V dB V ns ns A A ns V V mA dB V mA mA dB dB
DISABLE pin floating DISABLE pin = +VS
82 Differential mode Common mode
98 Output disabled 50% of DISABLE voltage to 10% of VOUT, VIN = 0.5 V 50% of DISABLE voltage to 90% of VOUT, VIN = 0.5 V DISABLE = +VS (enabled) DISABLE = -VS (disabled) VIN = -2.5 V to +2.5 V, G = +2 RL = 1 k RL = 100 Sinking/sourcing f = 1 MHz, DISABLE = -VS
-44
4.5 DISABLE = -VS +VS = 4 V to 6 V (input referred) -VS = -6 V to -4 V (input referred) 14.7 1.8 90 93
84 87
Rev. 0 | Page 3 of 20
ADA4899-1 SPECIFICATIONS WITH +5 V SUPPLY
VS = 5 V @ TA = 25C, G = +1, RL = 1 k to midsupply, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Offset Current Input Bias Offset Current Drift Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN DISABLE Input Threshold Voltage Turn-Off Time Turn-On Time Input Bias Current Input Bias Current OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rise/Fall) Output Voltage Swing Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions VOUT = 25 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 2 V step VOUT = 2 V step fC = 500 kHz, VOUT = 1 V p-p fC = 10 MHz, VOUT = 1 V p-p f = 100 kHz f = 100 kHz, DISABLE pin floating f = 100 kHz, DISABLE pin = +VS Min Typ 535 60 25 185 50 -100/-113 -89/-100 1.0 2.6 5.2 5 5 -6 -0.2 0.05 2.5 80 4 7.7 4.4 1.3 to 3.7 114 <2.4 100 60 16 -33 50/70 1.2 to 3.8 1.35 to 3.65 60/80 -48 12 16 1.7 18 210 -12 -1.5 Max Unit MHz MHz MHz V/s ns dBc dBc nV/Hz pA/Hz pA/Hz V V/C A A A nA/C dB k M pF V dB V ns ns A A ns V V mA dB V mA mA dB dB
DISABLE pin floating DISABLE pin = +VS
76 Differential mode Common mode
90 Output disabled 50% of DISABLE voltage to 10% of VOUT, VIN = 0.5 V 50% of DISABLE voltage to 90% of VOUT, VIN = 0.5 V DISABLE = +VS (enabled) DISABLE = -VS (disabled) VIN = 0 V to 2.5 V, G = +2 RL = 1 k RL = 100 Sinking/sourcing f = 1 MHz, DISABLE = -VS
-42
1.25 to 3.75 1.4 to 3.6
4.5 DISABLE = -VS +VS = 4.5 V to 5.5 V, -VS = 0 V (input referred) +VS = 5 V, -VS= -0.5 V to +0.5 V (input referred) 14.3 1.5 90 90
84 86
Rev. 0 | Page 4 of 20
ADA4899-1 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Power Dissipation Differential Input Voltage Differential Input Current Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 12.6 V See Figure 4 1.2 V 10 mA -65C to +150C -40C to +125C 300C 150C
The difference between the total drive power and the load power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power - Load Power)
V V PD = (VS x I S ) + S x OUT 2 RL
VOUT 2 - RL
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RMS output voltages should be considered. If RL is referenced to VS-, as in single-supply operation, then the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply:
PD = (VS x I S ) +
(VS / 4 )2
RL
In single-supply operation with RL referenced to VS-, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Soldering the exposed paddle to the ground plane significantly reduces the overall thermal resistance of the package. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle (e-pad) SOIC-8 (70C/W) and LFCSP (70C/W) packages on a JEDEC standard 4-layer board. JA values are approximations.
4.0 3.5
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4899-1 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4899-1. Exceeding a junction temperature of 150C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as
MAXIMUM POWER DISSIPATION (W)
3.0 2.5 2.0 1.5 1.0
05720-003
TJ = TA + (PD x JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT).
LFCSP AND SOIC
0.5 0.0 -40
-20
0
20 40 60 80 AMBIENT TEMPERATURE (C)
100
120
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADA4899-1 TYPICAL PERFORMANCE CHARACTERISTICS
3
NORMALIZED CLOSED-LOOP GAIN (dB)
VS = 5V RL = 1k VOUT = 25mV p-p
3 G = +1 G = -1
CLOSED-LOOP GAIN (dB)
G = +1 RL = 100 VOUT = 25mV p-p
0 G = +2 -3 G = +5 -6 G = +10
0
-3
VS = 5V
-6 VS = +5V -9
-9
05720-004
-12
1
10
100
1k
-12 10
100 FREQUENCY (MHz)
1k
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Gains
3
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 8. Small Signal Frequency Response for Various Supply Voltages
6
VS = 5V RL = 100 VOUT = 25mV p-p
G = +1
G = -1
CLOSED-LOOP GAIN (dB)
0
3
G = +1 RL = 1k VOUT = 25mV p-p
CL = 15pF RSNUB = 10
CL = 15pF CL = 5pF
0
-3 G = +10 -6
G = +2 G = +5
CL = 2pF CL = 0pF
-3
-6
-9
05720-005
-9
05720-032
-12
1
10
100
1k
-12 10
100 FREQUENCY (MHz)
1k
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Gains
3 T = +125C 0
CLOSED-LOOP GAIN (dB)
Figure 9. Small Signal Frequency Response for Capacitive Loads
5.0 4.5 4.0
VS = 5V VOUT = 25mV p-p G = +1 RL = 1k
G = +1 RL = 100
-3
PEAKING (dB)
G = +1 VS = 5V RL = 1k VOUT = 25mV p-p
T = -40C
3.5 3.0 2.5 2.0 1.5 G = +2 RL = 1k G = +1 RL = 1k RSNUB = 10
-6
-9
05720-006
1.0 0.5 0 0 5 10 15 20 25 30 35 40 45
05720-031
-12 10
100 FREQUENCY (MHz)
1k
CAPACITIVE LOAD (pF)
Figure 7. Small Signal Frequency Response for Various Temperatures
Figure 10. Small Signal Frequency Response Peaking vs. Capacitive Load for Various Gains
Rev. 0 | Page 6 of 20
05720-007
ADA4899-1
0.1 3 G = +1 VS = 5V RL = 100 VOUT = 1V p-p
0
CLOSED-LOOP GAIN (dB)
0
CLOSED-LOOP GAIN (dB)
-0.1
VOUT = 100mV p-p
VOUT = 4V p-p -3 VOUT = 7V p-p -6
-0.2 VOUT = 2V p-p -0.3
-0.4
-9
05720-010
-0.5
1
10 FREQUENCY (MHz)
100
-12
1
10
100
1k
FREQUENCY (MHz)
Figure 11. 0.1 dB Flatness for Various Output Voltages
3
Figure 14. Large Signal Frequency Response for Various Output Voltages
100 VS = 5V RL = 100 80 150
OPEN-LOOP PHASE (Degrees)
05720-030 05720-028
G = +1 RL = 1k VOUT = 2V p-p
180
0
CLOSED-LOOP GAIN (dB)
VS = 5V -3 VS = +5V -6
OPEN-LOOP GAIN (dB)
60
120
40
90
20
60
-9
05720-011
0
30
-12 10
100 FREQUENCY (MHz)
1k
-20 0.001
0.01
0.1
1
10
100
0 1k
FREQUENCY (MHz)
Figure 12. Large Signal Frequency Response for Various Supply Voltages
10 1k
Figure 15. Open-Loop Gain/Phase vs. Frequency
VOLTAGE NOISE (nV/ Hz)
CURRENT NOISE (pA/ Hz)
100
1
DISABLE = 5V 10
DISABLE = NC
05720-027
0.1 10
100
1k
10k
100k
1M
10M
100M
1 10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Voltage Noise vs. Frequency
Figure 16. Input Current Noise vs. Frequency
Rev. 0 | Page 7 of 20
05720-009
G = +2 VS = 5V RL = 150
ADA4899-1
-40 -50 G = +1 VS = 5V RL = 1k VOUT = 2V p-p -40 -50 G = +5 RL = 1k VS = 5V VOUT = 2V p-p
HARMONIC DISTORTION (dBc)
-60 -70 -80 -90
HARMONIC DISTORTION (dBc)
-60 -70 -80 HD2 -90 -100 HD3
05720-024
HD3 HD2
-100 -110
05720-021
-120 -130 0.1
-110 -120 0.1
1
10 FREQUENCY (MHz)
100
1
10 FREQUENCY (MHz)
100
Figure 17. Harmonic Distortion vs. Frequency
-40 -50
Figure 20. Harmonic Distortion vs. Frequency
-40 -50
G = +1 RL = 1k f = 5MHz
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
G = +5 VS = 5V RL = 100 VOUT = 2V p-p
-60 -70 -80 -90 -100 -110 -120 HD3
-60 -70 -80 -90 -100 -110 -120 0.1 HD2 SOIC -VS ON PIN 5
HD2 SOIC -VS ON PIN 4 HD2 LFCSP
HD2
HD3 LFCSP
HD3 SOIC -VS ON PIN 4 OR PIN 5
05720-043
05720-022
1
2
3
4
5
6
7
8
10
10
100
OUTPUT AMPLITUDE (V p-p)
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Output Amplitude
Figure 21. Harmonic Distortion vs. Frequency for Various Pinouts and Packages
-40 -50
-40 -50
G = +1 RL = 1k VS = 5V
HARMONIC DISTORTION (dBc)
-60 HD3 -70 VOUT = 2V p-p -80 -90 -100 -110 -120 0.1 VOUT = 1V p-p HD2
HARMONIC DISTORTION (dBc)
G = +1 VS = 5V RL = 100 VOUT = 2V p-p
-60 -70 -80 -90 -100
05720-044
HD2 LFCSP
HD2 SOIC
HD2
HD3
05720-023
-110 -120 0.1
HD3 LFCSP OR SOIC
1
10 FREQUENCY (MHz)
100
10
10
100
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency
Figure 22. Harmonic Distortion vs. Frequency for Both Packages
Rev. 0 | Page 8 of 20
ADA4899-1
0.10 0.08 0.06 G = +1 VS = 5V RL = 1k CL = 15pF CL = 5pF CL = 15pF RSNUB = 10 0.10 0.08 0.06 G = +1 VS = 5V RL = 1k
OUTPUT VOLTAGE (V)
0.04 0.02 0 -0.02 -0.04 -0.06
05720-041
OUTPUT VOLTAGE (V)
0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 CL = 5pF 0 5 TIME (ns) 10
05720-042
CL = 0pF
CL = 15pF CL = 0pF
-0.08 -0.10 0 5 TIME (ns) 10 15
CL = 15pF RSNUB = 10 15
Figure 23. Small Signal Transient Response for Various Capacitive Loads (Rising Edge)
0.08 0.06 0.04 G = +5 0.02 G = +10 0 -0.02 -0.04
05720-019
Figure 26. Small Signal Transient Response for Various Capacitive Loads (Falling Edge)
1.5 RL = 1k VS = 5V 1.0 G = +2
RL = 1k VS = 5V G = +2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.5
G = +10 G = +5
0
-0.5
-0.08
0
10
20
30
40
50 TIME (ns)
60
70
80
90
100
-1.5
0
10
20
30
40
50 TIME (ns)
60
70
80
90
100
Figure 24. Small Signal Transient Response for Various Gains
1.5
Figure 27. Large Signal Transient Response for Various Gains
1.5
G = +1 RL = 100 VS = 5V
G = +1 RL = 1k VS = 5V
1.0
1.0
OUTPUT VOLTAGE (V)
0.5 VS = +5V 0
OUTPUT VOLTAGE (V)
0.5 VS = +5V
0
-0.5
-0.5
-1.0
05720-017
-1.0
05720-018
-1.5
0
10
20
30
40
50 TIME (ns)
60
70
80
90
100
-1.5
0
10
20
30
40
50 TIME (ns)
60
70
80
90
100
Figure 25. Large Signal Transient Response for Various Supply Voltages
Figure 28. Large Signal Transient Response for Various Supply Voltages
Rev. 0 | Page 9 of 20
05720-013
-0.06
-1.0
ADA4899-1
1.5 0.3
10 G = +1 VS = 5V DISABLE = NC
1.0
0.2
OUTPUT IMPEDANCE ()
OUTPUT SETTLING (%)
1
0.5
VOLTAGE (V)
0.1 INPUT ERROR
0 OUTPUT -0.5
0
0.1
-0.1
0.01
05720-015
-1.0
-1.5
0
25
50
75 TIME (ns)
100
125
-0.3 150
05720-025
G = +1 VS = 5V RL = 1k
-0.2
0.001 0.001
0.01
0.1
1
10
100
1k
FREQUENCY (MHz)
Figure 29. Settling Time
1.5 0.3
100k
Figure 32. Output Impedance vs. Frequency
1.0 INPUT 0.5
VOLTAGE (V)
0.2
OUTPUT IMPEDANCE ()
G = +1 VS = 5V DISABLE = -5V
0.1
0 OUTPUT -0.5 ERROR
0
OUTPUT SETTLING (%)
10k
1k
-0.1
100
05720-014
-1.0
-1.5
0
25
50
75 TIME (ns)
100
125
-0.3 150
05720-026
G = +5 VS = 5V RL = 1k
-0.2
10 0.1
1
10 FREQUENCY (MHz)
100
1k
Figure 30. Settling Time
100k
Figure 33. Output Impedance vs. Frequency (Disabled)
-20 -30
INPUT IMPEDANCE ()
10k
COMMON-MODE REJECTION (dB)
G = +1 VS = 5V DISABLE = NC
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 10
G = +1 RL = 1k RF = 1k
1k
100
05720-016
VS = +5V
05720-020
VS = 5V 100 1k 10k 100k 1M 10M 100M
10 0.1
1
10 FREQUENCY (MHz)
100
1k
1G
FREQUENCY (Hz)
Figure 31. Input Impedance vs. Frequency
Figure 34. Common-Mode Rejection vs. Frequency
Rev. 0 | Page 10 of 20
ADA4899-1
0 -10 -20
SUPPLY REJECTION (dB)
500 N: 4651 MEAN: -4.92V SD: 29.22V VS = 5V
400
-30
COUNT
-40 -50 -60 +PSR -70 -80 -90 -100 0.001 0.01 0.1 1 10 100
05720-029
300
-PSR
200
100
05720-034
1k
0 -200
-150
-100
-50
0
50
100
150
200
FREQUENCY (MHz)
VOLTAGE OFFSET (V)
Figure 35. Power Supply Rejection
-22 -28 -34
ISOLATION (dB)
Figure 38. Input Offset Voltage Distribution (VS = 5 V)
VS = 5V DISABLE = -5V
500
N: 4655 MEAN: -34.62V SD: 28.94V VS = 5V
400
-40 -46 -52 -58
05720-012
COUNT
300
200
100
05720-035
-64 -70 0.1
1
10 FREQUENCY (MHz)
100
1k
0 -200
-150
-100
-50
0
50
100
150
200
VOLTAGE OFFSET (V)
Figure 36. Off Isolation vs. Frequency
N: 4653 MEAN: -0.083A SD: 0.13A VS = 5V
Figure 39. Input Offset Voltage Distribution(VS = 5 V)
700 600 500
COUNT
400 300 200
05720-033
100 0
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
INPUT BIAS CURRENT (A)
Figure 37. Input Bias Current Distribution
Rev. 0 | Page 11 of 20
ADA4899-1 TEST CIRCUITS
+VS 10F
RG RF +VS 10F
0.1F VIN 24.9 49.9 10F VOUT RL 0.1F
05720-045
0.1F VIN RT 10F 0.1F
05720-040
RSNUB
VOUT CL RL
-VS
-VS
Figure 40. Typical Noninverting Load Configuration
+VS AC 49.9
Figure 43. Typical Capacitive Load Configuration
+VS 10F
10
1k
10
1k
0.1F
VOUT 10 RL 10F 0.1F
05720-038
VOUT 10 RL AC 49.9
05720-039
-VS
-VS
Figure 41. Positive Power Supply Rejection
+VS 10F 1k 1k 0.1F VIN 53.6 1k 1k 10F VOUT RL 0.1F
05720-036
Figure 44. Negative Power Supply Rejection
-VS
Figure 42. Common-Mode Rejection
Rev. 0 | Page 12 of 20
ADA4899-1 THEORY OF OPERATION
The ADA4899-1 is a voltage feedback op amp that combines unity gain stability with a 1 nV/Hz input noise. It employs a highly linear input stage that can maintain greater than -80 dBc (@ 2 V p-p) distortion out to 10 MHz while in a unity gain configuration. This rare combination of low gain stability, input referred noise, and extremely low distortion is the result of Analog Devices proprietary op amp architecture and high speed complementary bipolar processing technology. The simplified ADA4899-1 topology, shown in Figure 45, is a single gain stage with a unity gain output buffer. It has over 80 dB of open-loop gain and maintains precision specifications such as CMRR, PSRR, and offset to levels that are normally associated with topologies having two or more gain stages. Both the SOIC and LFCSP have modified pinouts to improve heavy load second harmonic distortion performance. The intent of both is to isolate the negative supply pin from the noninverting input. The LFCSP accomplishes this by rotating the standard 8-lead package pinout counterclockwise by one pin. This puts the supply pins and output pins on one side of the package and the input pins on the other. The SOIC is slightly different with the intent of both isolating the inputs from the supply pins and giving the user the option of using the ADA4899-1 in a standard SOIC board layout with little or no modification. Taking the unused Pin 5 and making it a second negative supply pin allows for both an input isolated layout and a traditional layout to be supported.
DISABLE PIN
R1 CC RL
05720-060
gm
BUFFER
VOUT
Figure 45. ADA4899-1 Topology
A pair of internally connected diodes limits the differential voltage between the noninverting input and the inverting input of the ADA4899-1. Each set of diodes has two series diodes, which are connected in antiparallel. This limits the differential voltage between the inputs to approximately 1.2 V. All of the ADA4899-1 pins are ESD protected with voltage-limiting diodes connected between both rails. The protection diodes can handle 10 mA. Currents should be limited through these diodes to 10 mA or less by using a series limiting resistor.
PACKAGING INNOVATION
The ADA4899-1 is available in both a SOIC and a LFCSP, each of which has a thermal pad that allows the device to run cooler, thereby increasing reliability. To help avoid routing around this pad in board layout, both packages have an extra output pin on the opposite side of the packages for ease in connecting a feedback network to the inputs. The secondary output pin also isolates the interaction of any capacitive load on the output and the self-inductance of the package and bond wire from the feedback loop. While using the secondary output for feedback, inductance in the primary output helps to isolate capacitive loads from the output impedance of the amplifier.
A three-state input pin is provided on the ADA4899-1 for a high impedance disable and an optional input bias current cancellation circuit. The high impedance output allows several ADA4899-1s to drive the same ADC or output line timeinterleaved. Pulling the DISABLE pin low activates the high impedance state. See Table 7 for threshold levels. When the DISABLE pin is left floating (open), the ADA4899-1 operates normally. With the DISABLE pin pulled within 0.7 V of the positive supply, an optional input bias current cancellation circuit is turned on, which lowers the input bias current to less than 200 nA. In this mode, the user can drive the ADA4899-1 from a high dc source impedance and still maintain minimal output-referred offset without having to use impedance matching techniques. In addition, the ADA4899-1 can be ac-coupled while setting the bias point on the input with a high dc impedance network. The input bias current cancellation circuit doubles the input referred current noise, but this effect is minimal as long as the wideband impedances are kept low (see Figure 16).
Rev. 0 | Page 13 of 20
ADA4899-1 APPLICATIONS
UNITY GAIN OPERATION
The ADA4899-1 schematic for unity gain configuration is nearly a textbook example (see Figure 46). The only exception is the small 24.9 series resistor at the noninverting input. The series resistor is only required in unity gain configurations; higher gains negate the need for the resistor. In Table 4, it can be seen that the overall noise contribution of the amplifier and the 24.9 resistor is equivalent to the noise of a single 87 resistor. Figure 47 shows the small signal frequency response for the unity gain amplifier shown in Figure 46.
+VS 0.1F
CLOSED-LOOP GAIN (dB)
3
G = +1 RL = 100 50mV p-p
0 200mV p-p -3 100mV p-p -6 25mV p-p
-9
05720-063
-12
1
10
100 FREQUENCY (MHz)
1k
10k
Figure 47. Small Signal Frequency Response for Various Output Voltages
VOUT
VIN
24.9
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 4 provides a handy reference for determining various gains and associated performance. For noise gains greater than one, the series resistor RS is not required. Resistor RF and Resistor RG are kept low to minimize their contribution to the overall noise performance of the amplifier.
-VS
Figure 46. Unity Gain Schematic
Table 4. Conditions: VS = 5 V, TA = 25C, RL = 1 k
Gain +1 -1 +2 +5 +10 RF () 0 100 100 200 453 RG () NA 100 100 49.9 49.9 RS () 24.9 0 0 0 0 -3 dB SS BW (MHz) (25 mV p-p) 605 294 277 77 37 Slew Rate (V/s) (2 V Step) 274 265 253 227 161 ADA4899-1 Voltage Noise (nV/Hz) 1 2 2 5 10 Total Voltage Noise (nV/Hz) 1.2 2.7 2.7 6.5 13.3
05720-037
0.1F
Rev. 0 | Page 14 of 20
ADA4899-1
NOISE
To analyze the noise performance of an amplifier circuit, first identify the noise sources, then determine if the source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used, rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth). The noise model shown in Figure 48 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally specified referred to input (RTI), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise.
VN, R2 4kTR2 B VN, R1 4kTR1 VN, R3 4kTR3 R1 IN- VN R3 IN+ R2 GAIN FROM = "A" TO OUTPUT NOISE GAIN = NG = 1 + R2 R1 VOUT GAIN FROM = - R2 "B" TO OUTPUT R1
ADC DRIVER
The ultralow noise and distortion performance of the ADA4899-1 makes it an excellent candidate for driving 16-bit ADCs. The schematic for a single-ended input buffer using the ADA4899-1 and the AD7677, a 1 MSPS, 16-bit ADC, is shown in Figure 49. Table 5 shows the performance data of the ADA4899-1 and the AD7677.
+5V +5V 15 ANALOG + INPUT 25 IN+ AD7677 IN- REF -5V +2.5V REF
ADA4899-1
-5V +5V
2.7nF
15 ANALOG - INPUT
ADA4899-1
-5V
2.7nF
Figure 49. Single-Ended Input ADC Driver
Table 5. ADA4899-1, Single-Ended Driver for AD7677 16-Bit, 1 MSPS, fc = 50 kHz
Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR SNR
05720-070
A
VN2 + 4kTR3 + 4kTR1 RTI NOISE =
R2 R1 + R2
2
2
+ IN+2R32 + IN-2 R1 x R2 R1 + R2
+ 4kTR2
R1 R1 + R2
2
Measurement (dB) -116.5 -111.9 -108.6 +101.4 +92.6
RTO NOISE = NG x RTI NOISE
Figure 48. Op Amp Noise Analysis Model
The ADA4899-1 configured as a single-ended-to-differential driver for the AD7677 is shown in Figure 50. Table 6 shows the associated performance.
+5V +2.5V REF 590 ANALOG INPUT 590
All resistors have a Johnson noise that is calculated by
(4kBTR) where: k is Boltzmann's Constant (1.38 x 10-23 J/K). T is the absolute temperature in Kelvin. B is the bandwidth in Hz. R is the resistance in ohms. A simple relationship that is easy to remember is that a 50 resistor generates a Johnson noise of 1 nVHz at 25C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 4.
+2.5V REF 590 590 -5V
ADA4899-1 590
-5V 590 +5V
15 2.7nF
+5V IN+ AD7677 IN- REF -5V +2.5V
05720-061
15
ADA4899-1
2.7nF
Figure 50. Single-Ended-to-Differential ADC Driver
Table 6. ADA4899-1, Single Ended-to-Differential Driver for AD7677 16-Bit, 1 MSPS, fc = 500 kHz
Parameter THD SFDR SNR Measurement (dB) -92.7 +91.8 +90.6
Rev. 0 | Page 15 of 20
05720-062
25
ADA4899-1
DISABLE PIN OPERATION
The ADA4899-1 DISABLE pin performs three functions: enable, disable, and reduction of the input bias current. When the DISABLE pin is brought to within 0.7 V of the positive supply, the input bias current circuit is enabled. This reduces the input bias current by a factor of 100. In this state, the input current noise doubles from 2.6 pA to 5.2 pA/Hz. Table 7 outlines the DISABLE pin operation.
Table 7. DISABLE Pin Truth Table
Supply Voltage Disable Enable Low Input Bias Current 5 V -5 to +2.4 Open 4.3 to 5 +5 V 0 to 2.4 Open 4.3 to 5
An AD8137 differential amplifier is used as a level translator that converts the TTL input to a complementary 3 V output to drive the DISABLE pins of the ADA4899-1s. The transient response for the 2:1 mux is shown in Figure 52.
1
2
With a true output disable, the ADA4899-1 can be used in multiplexer applications. The outputs of two ADA4899-1s are wired together to form a 2:1 mux. Figure 51 shows the 2:1 mux schematic.
+5V 0.1F
Figure 52. ADA4899-1 2:1 Mux Transient Response
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the ADA4899-1 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier.
ADA4899-1
0.1F 1V p-p 15MHz 2.2F + DISABLE 50 1MHz 0V TO 5V 50 1k VOUT 50 RT 50 2k +5V 0.1F -5V
PCB Layout
Becausethe ADA4899-1 can operate up to 600 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4899-1 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on a SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads. The low distortion pinout of the ADA4899-1 reduces the distance between the output and the inverting input of the amplifier. This helps minimize the parasitic inductance and capacitance of the feedback path, which reduces ringing and second harmonic distortion.
AD8137
2.2F + -5V 1.02k VREF = 2.50V 2k
0.1F
DISABLE
+5V 0.1F
Power Supply Bypassing
ADA4899-1
0.1F -5V
05720-064
2V p-p 15MHz
Figure 51. ADA4899-1 2:1 Mux Schematic
Power supply bypassing for the ADA4899-1 has been optimized for frequency response and distortion performance. Figure 40 shows the recommended values and location of the bypass capacitors. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The 0.1 F capacitors shown in Figure 40 should be as close to the supply pins of the ADA4899-1 as possible. The electrolytic capacitors should be directly adjacent to the 0.1 F capacitors. The capacitor between the two supplies helps improve PSR and distortion performance. In some cases, additional paralleled capacitors can help improve frequency and transient response.
Rev. 0 | Page 16 of 20
05720-065
ADA4899-1 MUX
CH1 = 500mV/DIV CH2 = 5V/DIV 200ns/DIV
ADA4899-1
Grounding
Ground and power planes should be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input, output terminations, bypass capacitors, and RG should all be kept as close to the ADA4899-1 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. The ADA4899-1 packages feature an exposed paddle. For optimum electrical and thermal performance, solder this paddle to ground. For more information on high-speed circuit design, see A Practical Guide to High-Speed Printed-CircuitBoard Layout.
Rev. 0 | Page 17 of 20
ADA4899-1 OUTLINE DIMENSIONS
5.00 (0.197) 4.90 (0.193) 4.80 (0.189)
8 1 5 4
4.00 (0.157) 3.90 (0.154) 3.80 (0.150)
2.29 (0.092) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW
(PINS UP)
2.29 (0.092)
TOP VIEW
1.27 (0.05) BSC 1.75 (0.069) 1.35 (0.053) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY SEATING 0.10 PLANE 0.51 (0.020) 0.31 (0.012)
0.50 (0.020) x 45 0.25 (0.010)
8 0.25 (0.0098) 0 1.27 (0.050) 0.40 (0.016) 0.17 (0.0068)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 53. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] (RD-8-1) Dimensions shown in millimeters and (inches)
3.00 BSC SQ
0.60 MAX
0.50 0.40 0.30
PIN 1 INDICATOR
8
1
PIN 1 INDICATOR
TOP VIEW
2.75 BSC SQ
0.50 BSC
1.50 REF
5 4
1.89 1.74 1.59
0.90 MAX 0.85 NOM
12 MAX
0.70 MAX 0.65 TYP 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF
1.60 1.45 1.30
SEATING PLANE
Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters
Rev. 0 | Page 18 of 20
ADA4899-1
ORDERING GUIDE
Model ADA4899-1YRDZ 1 ADA4899-1YRDZ-R71 ADA4899-1YRDZ-RL1 ADA4899-1YCPZ-R21 ADA4899-1YCPZ-R71 ADA4899-1YCPZ-RL1
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD
Package Option RD-8-1 RD-8-1 RD-8-1 CP-8-2 CP-8-2 CP-8-2
Branding
HBC HBC
Ordering Quantity 1 1,000 2,500 250 1,500 5,000
Z = Pb-free part.
Rev. 0 | Page 19 of 20
ADA4899-1 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05720-0-10/05(0)
Rev. 0 | Page 20 of 20

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